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Title:
LAMINATED GRAIN BOUNDARY INSULATION TYPE SEMICONDUCTOR CERAMIC CAPACITOR
Document Type and Number:
Japanese Patent JPH0590062
Kind Code:
A
Abstract:

PURPOSE: To provide a laminated grain boundary insulation type semiconductor ceramic capacitor which ensures less fluctuation of electrical characteristics and high reliability in a laminated grain boundary insulation type semiconductor ceramic capacitor used in a veriety of electronic equipment.

CONSTITUTION: In a laminated grain boundary insulation type semiconductor ceramic capacitor in which, a plurality of layers of internal electrodes 5 is provided in such a manner that these electrodes alternately reach the end portions provided opposed thereto, in a grain boundary insulation type semiconductor ceramics 1 and external electrodes 3, 4 are provided to both end portions of these internal electrodes 5, the semiconductor ceramics 1 is turned semiconductive by reduction, sufficiently and uniformly up to its internal part by opening the holes 6 to the internal electrodes 5 up to the total area of 5 to 30% for the effective electrode area. Thereby, fluctuation of electrical characteristics can be lowered and reliability can be improved.


Inventors:
SHIRAISHI KAORI
TAKAMI AKIHIRO
OGOSE YOICHI
WAKAHATA YASUO
UENO IWAO
Application Number:
JP24727291A
Publication Date:
April 09, 1993
Filing Date:
September 26, 1991
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01G4/12; H01G4/30; (IPC1-7): H01G4/12; H01G4/30
Attorney, Agent or Firm:
Akira Kobiji (2 outside)