Title:
Lamination LSI chip
Document Type and Number:
Japanese Patent JP6099192
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a stack LSI chip capable of reducing parasitic impedance produced between a communication driver circuits and capable of easily grasping the parasitic impedance.SOLUTION: Each LSI chip 10 in a stack LSI chip 11 includes a bidirectional communication driver circuit 51 to communicate between the LSI chips 10 through a through electrode 20, for each through electrode 20. The communication driver circuit 51 is disposed in a chip central area P in the vicinity of the corresponding through electrode 20.
Inventors:
Fumito Imura
Hiroshi Nakagawa
Masahiro Aoyagi
Matsumoto Yukyo
Yuya Hagimoto
Hiroyuki Uchida
Hiroshi Nakagawa
Masahiro Aoyagi
Matsumoto Yukyo
Yuya Hagimoto
Hiroyuki Uchida
Application Number:
JP2012272774A
Publication Date:
March 22, 2017
Filing Date:
December 13, 2012
Export Citation:
Assignee:
National Institute of Advanced Industrial Science and Technology
Tops Systems Co., Ltd.
Tops Systems Co., Ltd.
International Classes:
H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP2012119022A | ||||
| JP2010098318A | ||||
| JP2006108328A |
Attorney, Agent or Firm:
Yoshiyuki Inaba
Toshifumi Onuki
Takahiro Kobuki
Toshifumi Onuki
Takahiro Kobuki
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