Title:
LARGE-SCALE INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS57204140
Kind Code:
A
Abstract:
PURPOSE:To check each circuit block of the inside corresponding to the changeover of a plurality of test modes by the logic level of a pin for controlling a test by changing over the test modes by the logic level. CONSTITUTION:When checking the output of the circuit block 11, the controlling pins 6, 7 for the test are each made the L and H levels, input pins 1, 2 are selected as the input of an input circuit 13, and the output expectation value of the circuit block 10 is inputted from the input pins 1, 2 and output is checked. When checking the output of the circuit block 10, the controlling pins 6, 7 for the test are each made the H and L levels, input pins 1, 2, 3 are selected as the input of an input circuit 12, and the output expectation value of the circuit block 9 may be inputted from the input pins 1, 2, 3. Accordingly, when checking each circuit block 9, 10, 11, the logic levels of the pins 6, 7 for controlling the test are changed, the input circuits are changed over and output is checked.
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Inventors:
TAKEGUCHI YORIYASU
Application Number:
JP8904081A
Publication Date:
December 14, 1982
Filing Date:
June 10, 1981
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/822; G01R31/317; H01L21/66; H01L27/04; (IPC1-7): H01L27/04
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