To provide a large-scale semiconductor integrated circuit device which has a small design margin on an operating frequency, etc., and has a high yield by being equipped with a plurality of clock trees having an appropriate arriving delay time according to the position of each input circuit.
The large-scale semiconductor integrated circuit device comprises an original oscillator which develops a basic clock for operating a synchronous circuit; functional blocks referring to logics used for a CPU, a memory, or the other specifically intended purpose; the clock trees which are inputted with the clock developed by the original oscillator 10 and drive the functional blocks; and a non-synchronous I/F block 15 constructed of a non-synchronous FIFO circuit or the like which transfers information between the functional blocks. Arriving delay times of the clock trees are properly set according to the position of the corresponding functional block on the LSI.
Masayoshi Kanda
Akio Miyao