ラッチ回路および4相クロック発生器

Title:

ラッチ回路および4相クロック発生器

Document Type and Number:

Japanese Patent JP4152969

Kind Code:

B2

Abstract:

A latch circuit (100) includes a voltage driven type data reading unit (101) and a voltage driven type data holding unit (102), and operates based on a clock signal (CK, CKX) that is supplied from an outside source. The data reading unit (101) reads both first input data (D), and second input data (DX), and outputs both first output data (Q), and second output data (QX), based on both the first input data and the second input data, while the data holding unit (102) holds both the first output data and the second output data. Both the first input data and the second input data (D,DX) are differential signals, and both the first output data and the second output data (Q,QX) are differential signals that have phases that are inverted.

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Inventors:

Marutani Masazumi

Application Number:

JP2005159460A

Publication Date:

September 17, 2008

Filing Date:

May 31, 2005

Export Citation:

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