To reduce a circuit area and a test time in the case of conducting a scanning test by latching input data synchronously with a prescribed clock signal and selecting a latch operation or a through-buffer operation of a through- buffer.

With a control signal S set to 0, when a value of a latch enable signal G received by a NAND circuit 11 is 0, a value D1 of a data signal received by a D input 13C is outputted to a Q output 17. When the value of the latch enable signal G changes to 1, even when the value of the data signal received by a D input 13C changes to D2, an output from the Q output 17 is not immediately changed but keeps the value D1. In this case, the value D2 at the D input 13C is outputted to the Q output 17 when the latch enable signal G changes to 0. Furthermore, the control signal S is set to 1, even when the latch enable signal G is at '1', when the D input changes to a value D3, the value is outputted to the output Q.