Title:
LATCH CIRCUIT
Document Type and Number:
Japanese Patent JPH07240671
Kind Code:
A
Abstract:
PURPOSE: To provide the latch circuit of short decomposition time. CONSTITUTION: This CMOS latch circuit 202 is provided with a second feedback inverter 208 and a switching circuit, and when a latch is loaded, the second feedback inverter 208 is switched to the outside of the circuit. First circuit constitution uses a single PFET as the switching circuit and second circuit constitution incorporates an NFET transistor 210 parallelly to the PFET. In third circuit constitution, the switching circuit does not switch the output signals of the second feedback inverter 208, switches power to the second feedback inverter 208 or from the second feedback inverter 208 and reduces the input capacitance of the latch.
Inventors:
GOODON DABURIYU MOTOREE
PIITAA JIEE MEIYAA
BURAIAN SHII MIRAA
PIITAA JIEE MEIYAA
BURAIAN SHII MIRAA
Application Number:
JP4911895A
Publication Date:
September 12, 1995
Filing Date:
February 14, 1995
Export Citation:
Assignee:
HEWLETT PACKARD CO
International Classes:
H03K3/037; H03K3/356; (IPC1-7): H03K3/356
Attorney, Agent or Firm:
Hideo Ueno