PURPOSE: To simplify the circuit by providing the MISFET in parallel with the precharge MISFET, on the input side of the clocked inverter circuit, and controlling by the output of the inverter circuit.

CONSTITUTION: The MISFETQ2 controlled by the output of the clocked inverter circuit IN1 which inputs the dynamic output signal OUT of the ROM, and the MISFETQ1 controlled by the precharge signal P are connected in parallel. And the clock pulse ' of the circuit IN1 rises later than the timing by which the FETQ1 is turned off and the output level is obtained, and rises by sunchronizing with the next precharge operation start timing. Accordingly, the same logical design as the static ROM can be executed and the circuit can be designed easily by only adding a simple circuit to the dynamic ROM.