PURPOSE: To obtain a high speed circuit by providing the 1st inverter outputting a signal outputted from a latch control section inversely and the 2nd inverter inverting the said output and feeding it back to the input of the 1st inverter.

CONSTITUTION: A PMOS transistor (TR) 20a and an NMOSTR 204 act like a resistive element at the on-state. In impressing a signal L to a latch control terminal 5, the NMOS TR 20 is turned off. When the latch output terminal 4 is at a signal H level, the PMOSTR 202 is turned off and the NMOS TR 203 is turned on, the the latch output terminal 4 keeps a signal H to bring the signal level of the terminal 3 to L level. When the latch output terminal 4 is in the signal L level conversely, the PMOS TR 202 is turned on and the NMOS TR 203 is turned off and the latch output terminal 4 keeps the signal L to bring the terminal 3 to the signal H level. That is, positive feedback is applied by the inverter circuit 30 and a series circuit composing of MOSTRs 201, 202, 203, 204, then the signal at the latch output terminal 4 is kept.