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Title:
LATCH CIRCUIT
Document Type and Number:
Japanese Patent JPS6468012
Kind Code:
A
Abstract:

PURPOSE: To improve the dropping voltage characteristic by operating an output transistor TR with the base potential self-bias in the reset state, namely, the thyristor operation state.

CONSTITUTION: When a voltage in the high level is applied to an input terminal 1, an NPN TR Q2 is operated to drive PNP TRs Q3 and Q4. The circuit consisting of TRs Q2 and Q3 and resistances R2∼R4 is a latch circuit: though a set terminal goes to the low level after operation of TRs Q2∼Q4, TRs Q4 and Q5 are kept operated because the TR Q2 is driven by the TR Q3, and a TR Q6 is cut off and an output terminal 3 goes to the high level. When a voltage in the high level is applied to an input terminal 2 and a TR Q1 is made conductive and the TR Q2 is cut off, the TR Q6 is made conductive because TRs Q3∼Q5 are cut off, and the output terminal goes to the low level. Thus, the dropping voltage characteristic is improved.


Inventors:
IWATA HIROMITSU
MORI KAZUHIRO
Application Number:
JP22587987A
Publication Date:
March 14, 1989
Filing Date:
September 08, 1987
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
H03K3/286; (IPC1-7): H03K3/286
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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