Title:
ラッチ構造、周波数分周器、及びそれらを動作させる方法
Document Type and Number:
Japanese Patent JP2012503443
Kind Code:
A
Abstract:
A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.
Inventors:
Jean, kun
Barnet, Kenneth
Barnet, Kenneth
Application Number:
JP2011528012A
Publication Date:
February 02, 2012
Filing Date:
September 18, 2009
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
H03K3/356; H03K3/037; H03K23/00
Domestic Patent References:
| JPH0595281A | 1993-04-16 | |||
| JPH0629791A | 1994-02-04 | |||
| JPH118550A | 1999-01-12 | |||
| JP2003512752A | 2003-04-02 |
Foreign References:
| US20060168487A1 | 2006-07-27 | |||
| US6239640B1 | 2001-05-29 |
Attorney, Agent or Firm:
Kurata Masatoshi
Takakura Shigeo
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takakura Shigeo
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori