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Patent Searching and Data


Title:
LATCH TYPE INVERTER CIRCUIT
Document Type and Number:
Japanese Patent JPS5817726
Kind Code:
A
Abstract:

PURPOSE: To obtain an output waveform at a desired delay time even with fluctuated power supply voltage, by providing a feedback circuit in which self- bias is changed in response to prechanrge level, to a connecting point of two MOSFETs constituting a delay section.

CONSTITUTION: At waiting a terminal N7 is precharged to a level lower by one step than that of a power supply voltage and gm of a MOSFETQ15 has a large value with high gate voltage. Thus, when an input signal in is applied at the operation, the level of a terminal A determined with the ratio of gm of the MOSFETs Q15 and Q17 is high. Thus, a voltage at a terminal N6 which is determined with the ratio of gm of the MOSFETs Q16 and Q17 connected in series with the MOSFETQ14 also reaches a threshold level at earlier point and a MOSFETQ19 turns on earlier. Then, even if the power supply voltage is fluctuated, the FF is inverted with a specified delay time and the output waveform out of the driving section II can be turned on at the point of time. That is, useless delay of output waveform can be decreased.


Inventors:
JIYOUKOU RIICHI
SATOU TAKASHI
Application Number:
JP11503281A
Publication Date:
February 02, 1983
Filing Date:
July 24, 1981
Export Citation:
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Assignee:
HITACHI LTD
HITACHI MICROCUMPUTER ENG
International Classes:
H03K3/356; H03K19/096; (IPC1-7): H03K19/096
Attorney, Agent or Firm:
Toshiyuki Usuda