LATERAL BIPOLAR TRANSISTOR AND ITS FORMATION METHOD

Title:

LATERAL BIPOLAR TRANSISTOR AND ITS FORMATION METHOD

Document Type and Number:

Japanese Patent JPH0621073

Kind Code:

A

Abstract:

PURPOSE: To attain miniaturization of a lateral bipolar transistor and the reduction of parasitic resistance by solving the problem of allowable alignment difference in the manufacturing processes of this transistor. CONSTITUTION: This process for manufacturing a lateral bipolar transistor is provided with a step (i) for successively forming an epitaxial layer 11, a silicon oxide layer 12, a silicon nitride layer 13 and a mask layer 14 on a silicon wafer 10, a step (ii) for forming an opening 26 for an emitter or collector region surrounded by channels specified by an isolation region on the mask layer through a single mask operation, and a step (iii) for providing an isolation means in the isolation region by processing the respective layers through selective etching and doping, and for providing a high-level conductive doped region inside the emitter or collector region.

Inventors:

DEYUKASU JIYANNPOORU
GIYUURU PATORITSUKU

Application Number:

JP4732793A

Publication Date:

January 28, 1994

Filing Date:

February 12, 1993

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Assignee:

MOTOROLA SEMICONDUCTEURS

International Classes:

H01L29/73; H01L21/331; H01L21/761; H01L21/8224; H01L29/08; H01L29/735; (IPC1-7): H01L21/331; H01L29/73

Attorney, Agent or Firm:

Yoshiaki Ikeuchi

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