Title:
レイアウト設計装置、レイアウト設計方法、レイアウト設計プログラム、および記録媒体
Document Type and Number:
Japanese Patent JP4391300
Kind Code:
B2
Abstract:
A layout designing apparatus includes an input unit that receives an input of a frame having a boundary scan register, a placing unit that places an I/O macro to be connected to a signal terminal for propagating other signal than a test signal in an arbitrary I/O macro placement area of the frame input, a determining unit that determines whether a frame terminal at an arbitrary terminal position in the frame matches with at least one of a test terminal for propagating the test signal in the frame input and a signal terminal to be connected to the I/O macro placed, and a replacing unit that replaces, based on a result of determining by the determining unit, the I/O macro placed with either of a shared I/O macro and a test-only I/O macro.
More Like This:
| WO/2003/046591 | MULTI-ENVIRONMENT TESTING WITH A RESPONDER |
| JPH10303371 | SEMICONDUCTOR INTEGRATED CIRCUIT |
| JPS52123662 | IC INSPECTION CIRCUIT IN ELECTRONIC WATCHES |
Inventors:
Seiko Osaki
Abe Koji
Jin Watanabe
Abe Koji
Jin Watanabe
Application Number:
JP2004123548A
Publication Date:
December 24, 2009
Filing Date:
April 19, 2004
Export Citation:
Assignee:
Fujitsu Microelectronics Limited
International Classes:
G01R31/3185; G01R31/28; G06F9/45; G06F17/50; G06F9/455; H01L21/82; H01L21/822; H01L27/04
Domestic Patent References:
| JP9145785A | ||||
| JP2003100878A | ||||
| JP2002026129A |
Attorney, Agent or Firm:
Akinori Sakai