Title:
LAYOUT DESIGN METHOD AND DESIGN DEVICE IN TEST FACILITATING SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3190821
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the total sum of scan pass length in the layout design of a test facilitating semiconductor integrated circuit having plural scan passes.
SOLUTION: After the arrangement of respective cells is decided by an arranging device 102, a node assigning device 106 executes assignment to the respective scan passes, that is, a scan-in terminal, a scan-out terminal and scan FF so as to reduce the total of scan pass length as much as possible. Then, a route optimizing device 107 decides and improves the connection order of scan FF concerning the respective scan passes so as to permit their length to be min. A node converting device 108 exchanges the scan FF, the scan-in terminal and the scan-out terminal among the plural scan passes so as to reduce the total sum of scan pass length.
Inventors:
Susumu Kobayashi
Application Number:
JP11891796A
Publication Date:
July 23, 2001
Filing Date:
May 14, 1996
Export Citation:
Assignee:
NEC
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Attorney, Agent or Firm:
Naoki Kyomoto