Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
LAYOUT DESIGNING METHOD OF INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH03253059
Kind Code:
A
Abstract:

PURPOSE: To eliminate a need to reexecute an automatic arrangement and interconnection program when several kinds of IC's which are partially different are designed and to reduce a production cost while reliability is being increased by a method wherein individual models are designed so as to fulfill their function when a switch of a cell for switching use is changed over.

CONSTITUTION: When a logic circuit is designed, individual models A, B, C are designed so as to fulfill their function when a switch of a cell 25 for switching use is changed over. That is to say, when one cell 125A out of layout cells 125A to 125C corresponding to the cell 25 is decided, its interconnection length becomes clear; as a result, the signal delay time is presumed accurately by means of information on the interconnection length. Then, when a mask data for an IC production process is formed, the cells 125A, 125B, 125C are arranged according to the difference in the models A, B, C in the part of the cell 125A. This arrangement operation is enough only by arranging any of insulators 411 to 413 in the part of the cell 125A of an insulator layer 401. That is to say, since a layer which is different by the difference in the models is only the layer 401, the mask production process can be made common.


Inventors:
NISHII OSAMU
UCHIYAMA KUNIO
AOKI HIROKAZU
Application Number:
JP4936190A
Publication Date:
November 12, 1991
Filing Date:
March 02, 1990
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HITACHI LTD
International Classes:
H01L21/822; G06F17/50; H01L21/82; H01L27/04; (IPC1-7): G06F15/60; H01L21/82; H01L27/04
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)