Title:
レイアウト方法及び半導体装置の製造方法
Document Type and Number:
Japanese Patent JP5699826
Kind Code:
B2
Inventors:
Takanori Hiramoto
Toshio Hino
Tsuyoshi Sakata
Hiroshi Mizuno
Katsuya Ogata
Toshio Hino
Tsuyoshi Sakata
Hiroshi Mizuno
Katsuya Ogata
Application Number:
JP2011142067A
Publication Date:
April 15, 2015
Filing Date:
June 27, 2011
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
H01L21/82; G03F1/70; H01L21/822; H01L27/04
Domestic Patent References:
| JP2012929A | ||||
| JP2011054859A | ||||
| JP2011044222A | ||||
| JP2010509783A |
Foreign References:
| WO2009044434A1 | ||||
| WO2005041301A1 |
Attorney, Agent or Firm:
Takeshi Hattori