Title:
LAYOUT PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JPS6432385
Kind Code:
A
Abstract:
PURPOSE:To avoid manual correction of layout to reduce the man-hour for design by providing a means which calculates the wiring length of a designated net and a means which moves blocks so that the wiring length is within an allowable range. CONSTITUTION:A wiring length calculating means 1 calculates a wiring length L of a designated net in accordance with logical connection information of an electric circuit and block layout information which are inputted from a CPU. A wiring length comparing means 21 in a block rearranging means 2 compares the wiring length L with an allowable wiring length of the designated net given from the external. When the wiring length L is longer than the allowable value as the comparison result, a wiring length shortening block moving means 22 in the rearranging means 2 moves blocks so that the wiring length of the net is shortened to be within the allowable range. When the wiring length L is shorter than the allowable value, a wiring length L is shorter than the allowable value, a wiring extending block moving means 23 in the rearranging means 2 moves blocks so that the wiring length of the net is extended to be within the allowable range.
Inventors:
MABUKURO TAMAKI
Application Number:
JP18966187A
Publication Date:
February 02, 1989
Filing Date:
July 28, 1987
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F1/10; G06F17/50; (IPC1-7): G06F15/60
Attorney, Agent or Firm:
Junichi Kawahara