Title:
LAYOUT AND ROUTING
Document Type and Number:
Japanese Patent JPH05198676
Kind Code:
A
Abstract:
PURPOSE: To reduce a design time consumed for trial of an automatic layout and routing by making it possible to know whether or not wiring delay exists which can not be restrained through any wiring without waiting for a routing process to be finished.
CONSTITUTION: Judgment can be performed without waiting for a routing process to be finished whether or not a semiconductor integrated circuit device can be designed from provided layout by extracting a Manhattan wiring length from layout results (S5), by carrying out simulation after layout (S6), and by judging whether or not expected results can be obtained by simulation (S7).
Inventors:
TANAKA YOSHIHIRO
Application Number:
JP3258592A
Publication Date:
August 06, 1993
Filing Date:
January 23, 1992
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/82; G06F17/50; (IPC1-7): G06F15/60; H01L21/82
Attorney, Agent or Firm:
Miyazono Junichi