Title:
LAYOUT VERIFICATION METHOD AND CIRCUIT SIMULATION METHOD
Document Type and Number:
Japanese Patent JPH0944559
Kind Code:
A
Abstract:
To automatically verify an LVS on condition that a SPICE net list is extracted from a layout pattern.
An external SPICE net list extraction tool 1 extracts the SPICE net list 4 from the layout pattern 3 and a net lister 5 which is internally provided extracts a circuit diagram net list 6 from circuit diagram data 2; and then a net comparator 7 which is internally provided compares the circuit diagram net list 6 and SPICE net list 4 with each other to verify the layout pattern 3.
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Inventors:
KITAO KATSUYUKI
Application Number:
JP21122795A
Publication Date:
February 14, 1997
Filing Date:
July 27, 1995
Export Citation:
Assignee:
RICOH KK
International Classes:
G06F17/50; (IPC1-7): G06F17/50
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