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Title:
LEAD FRAME FOR SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPS62144349
Kind Code:
A
Abstract:

PURPOSE: To arrange bonding regions at small pitches, and to shorten distances reaching the bonding regions from semiconductor chips by reducing the width of inner leads and forming the bonding regions occupying the nose sections of the inner leads through coining.

CONSTITUTION: A plurality of inner leads 3a, nose sections thereof function as bonding regions 6a to wires W for connection, are disposed approximately radially, inward directing the bonding regions 6a, and the width of sections connected to the bonding regions 6a is made smaller than width required for bonding the wires W for connection and the bonding regions 6a are shaped, ensuring required width through coining working in the inner leads 3a. When the bonding regions 6a in the inner leads 3a, the nose sections thereof serve as the bonding regions 6a to the wires W for connection are formed through coining working, grooves 8 are shaped to surfaces on the coining sides of the root sections of coining regions prior to coining working.


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Inventors:
TSUJI KAZUTO
AOKI TSUYOSHI
SUGIURA RIKIO
Application Number:
JP28620185A
Publication Date:
June 27, 1987
Filing Date:
December 19, 1985
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L23/50; H01L23/495; (IPC1-7): H01L23/48
Attorney, Agent or Firm:
Sadaichi Igita



 
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