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Title:
LEAD FRAME FOR SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2001326312
Kind Code:
A
Abstract:

To provide a new QFP type lead frame for semiconductor integrated circuits that prevents wire-bonding properties and the joint properties with the terminal of an external circuit substrate from being lost and a migration phenomenon from being generated, allowing armor solder-plating processes to be abbreviated, is reliable, and can be manufactured inexpensively.

In the lead frame that is used for a semiconductor integrated circuit, base Ni plating that is as thick as 0.3-1.5 μm and is superb in flexibility is performed to a material surface, and then a ring-like 0.2-5 μm Ag plating, and extremely thin Au plating that is as thick as 0.003-0.02 μ or extremely thin hard Au alloy plating containing either or both of 0.01-3 wt.% Ni and Co are performed to the tip of all inner leads to be subjected to wire bonding, and an outer lead part, respectively.


Inventors:
OTAKE KOJI
KAWAKAMI YOSHIMI
Application Number:
JP2000183714A
Publication Date:
November 22, 2001
Filing Date:
May 17, 2000
Export Citation:
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Assignee:
AZUMA DENKA KK
International Classes:
C25D7/00; C23C28/00; H01L23/50; C25D7/12; (IPC1-7): H01L23/50; C23C28/00