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Title:
LEAD FRAME FOR SEMICONDUCTOR
Document Type and Number:
Japanese Patent JPS6392047
Kind Code:
A
Abstract:

PURPOSE: To eliminate wire breakdown faults at the time of wire bonding, by connecting an island, on which a semiconductor chip is mounted with a supporting piece as a unitary body, and bonding the tips of inner leads with a flat connector in an electrically insulated manner.

CONSTITUTION: On the surface of a flat connector 4 having a U shape as viewed on a horizontal plane, electrically excellent conductor layers comprising a copper foil layer 15, a silver plated layer 16 and the like are formed. The flat connector 14 is arranged so as to stride on the upper surface of a supporting piece and the upper surfaces of the vicinities of the tip parts of a plurality of inner lead pads. They are bonded with a bonding agent having electric insulating property so that they are not separated. The surface of the electrically excellent conductor layers on the flat linking body 14 and the supporting piece 10 undergo wire bonding with wire 17 such as gold wire. Thus the tips of all the inner lead parts 13 can be moved up and down only as a unitary body with the flat connector 14. In wire bonding, careless wire breakdown faults do not occur.


Inventors:
UESUGI KENJI
Application Number:
JP23770486A
Publication Date:
April 22, 1988
Filing Date:
October 06, 1986
Export Citation:
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Assignee:
ROHM CO LTD
International Classes:
H01L23/50; H01L21/60; (IPC1-7): H01L21/60; H01L23/50
Attorney, Agent or Firm:
Akio Ishii



 
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