Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3216615
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To shorten a process of a semiconductor device for manufacturing a logic circuit and a non-volatile memory on a single substrate by contriving a write voltage and an erase voltage applied to the non-volatile memory to reduce the required breakdown voltage of the non-volatile memory to the same level as that of the logic circuit.
SOLUTION: A deep first well 42 of a second conductive type is selectively formed on a semiconductor substrate 41 of a first conductive type. A third conductive well 43-2 of a first conductive type if formed in a place other than the place of the semiconductor substrate 41 where the first well 42 is formed. Here, a second well 43-1 and the third well 43-2 are formed at the same time by reducing the required breakdown voltage of a memory cell with some contrivance to the operating voltage of a non-volatile memory. Since the well 43-2 for logic circuit and a well 43-3 for the non-volatile memory are formed at the same time, a manufacturing process of a semiconductor device having the logic circuit and the non-volatile memory on the single substrate can be shortened.
Inventors:
Kunio Kokubun
Application Number:
JP27786298A
Publication Date:
October 09, 2001
Filing Date:
September 30, 1998
Export Citation:
Assignee:
NEC
International Classes:
G11C16/04; H01L21/8238; H01L21/8247; H01L27/092; H01L27/10; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; G11C16/04; H01L21/8238; H01L27/092; H01L27/10; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP1056158A | ||||
| JP7245352A | ||||
| JP528784A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)