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Title:
LEVEL ADJUSTER
Document Type and Number:
Japanese Patent JPS5582518
Kind Code:
A
Abstract:

PURPOSE: To avoid the feeling of abnormal sound at signal interruption, by changing the input digital signal with the digital signal generator according to the attenuation characteristics preset.

CONSTITUTION: When the instruction switch 14 is closed, pulse is fed to P-ROM20 in the preset interval from the clock generator 19. At P-ROM20, every input pulse, preset attenuation is produced and fed to the digital subtractor 15, and the differential signal component with the input digital signal from the terminal 11 passes through the data selector 16. Further, when the attenuation of the digital signal is greater than the input digital signal, the carryout of the subtractor 15 is 0 and the data selector 16 feeds the output of all 0 to the terminal 12.


Inventors:
MATSUSHIMA KOUJI
SHIMEKI TAIJI
KIHARA NOBUYOSHI
Application Number:
JP15702278A
Publication Date:
June 21, 1980
Filing Date:
December 19, 1978
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G11B20/10; H03G3/00; H03G3/02; (IPC1-7): G11B5/09; H03G3/00
Domestic Patent References:
JPS50131437A1975-10-17