To keep a good balance between a fall delay time characteristic and a rise delay time characteristic of an output signal even when at least one of amplitude voltages of an input signal and the output signal is changed in a level conversion circuit.
When an amplitude voltage (first power supply voltage VDDL) of an input signal of an input terminal in is changed to a high voltage, and an amplitude voltage (second power supply voltage VDDH) of an output signal of an output terminal out is changed to a low voltage, a fall delay time of the signal from the output terminal out easily becomes longer than a rise delay time. However, since an inversion input signal through an inverter I1 is inputted to a level conversion portion L and to a gate of an N type transistor N3, the N type transistor N3 is turned ON when the input signal of the input terminal in falls, current is supplied to an output node n3 of the level conversion portion L from the second power supply voltage DDDH, and a conversion to an H level at the level conversion portion L is assisted.
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NAKANISHI KAZUYUKI
YAMAMOTO HIROO
HIRATA AKIO
HATSUDA TSUGUYASU
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Takashi Goto
Iseki Katsumori