Title:
LEVEL CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JPH01165208
Kind Code:
A
Abstract:
PURPOSE:To obtain a level conversion circuit in which no level shift quantity depends on a temperature by obtaining an output signal from the connection point of a resistor to a junction type FET at the current control side of a current mirror circuit. CONSTITUTION:First and second FETs Q6 and Q7 are connected in parallel, and input signals V2 and V1 are supplied to the gate electrodes of those FETs, and also, one ends of first and second resistors R3 and R4 are connected to the output electrodes of those FETs, and third and fourth FETs Q8 and Q9 which constitute the current mirror circuit are connected to the other ends of those resistors R3 and R4, and an output voltage V0 can be taken out from the connection point of the first resistor R3 to the third FETQ8. In such a way, no change in the level shift quantity due to temperature change is generated, and also, it is possible to respond to the differential output of a differential amplifier, and to increase output amplitude.
Inventors:
TAKAHASHI KENJI
Application Number:
JP32342487A
Publication Date:
June 29, 1989
Filing Date:
December 21, 1987
Export Citation:
Assignee:
NIPPON MINING CO
International Classes:
H03F3/343; H03F1/30; H03F3/34; H03K5/02; H03K19/00; H03K19/0185; (IPC1-7): H03F1/30; H03F3/343; H03K5/02; H03K19/00
Attorney, Agent or Firm:
Tsuchiya Masaru
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