Title:
LEVEL CONVERTER CIRCUIT
Document Type and Number:
Japanese Patent JP3233321
Kind Code:
B2
Abstract:
PURPOSE: To realize high speed operation and low power consumption for the circuit.
CONSTITUTION: CMOS inverters 3, 4 with a low threshold voltage are connected in cascade and a CMOSFET M5 with a high threshold voltage is connected in series between a common connecting source of PMOSFETs of the CMOS inverters 3, 4 and a power supply terminal. Complementary signals obtained by both CMOS inverters 3, 4 are given to a latch circuit 5 comprising CMOS inverters with a high threshold voltage and an output of the latch circuit 5 is led to an output terminal via CMOS inverters 6, 7 with a high threshold voltage in cascade connection.
Inventors:
Takakuni Doseki
Application Number:
JP4334594A
Publication Date:
November 26, 2001
Filing Date:
February 18, 1994
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
H03K19/0185; G11C11/407; (IPC1-7): H03K19/0185
Attorney, Agent or Firm:
Tsuneaki Nagao