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Title:
LEVEL CONVERTING CIRCUIT
Document Type and Number:
Japanese Patent JPS60217723
Kind Code:
A
Abstract:

PURPOSE: To improve the matching with other circuit parts with low power and high speed operation by combining logical circuits to a CMOS constitution level converter so as to control the converter thereby eliminating the contention state of the converter without requiring considerable change of element size.

CONSTITUTION: An MOS13 is turned on when an MOS11 is turned on, but since an MOS15 is turned off, no contention is caused. Further, the MOS13 is turned off when the MOS15 is turned on and no contention is caused. On the other hand, both MOS14, 16 are turned on when an MOS12 is turned off and the potential at a point Q falls down rapidly to Vss. Since an output X of a NAND17 rises when the MOS16 is turned off, the potential at the point Q falls down sufficiently. When the MOS16 is turned off, the point Q reaches the floating state and the low potential is kept by the floating capacitance at the point Q. Thus, the desired operation with no contention is attained in this way.


Inventors:
EBIHARA HEIHACHIROU
Application Number:
JP7424784A
Publication Date:
October 31, 1985
Filing Date:
April 13, 1984
Export Citation:
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Assignee:
CITIZEN WATCH CO LTD
International Classes:
H03K5/02; H03K3/356; (IPC1-7): H03K5/00