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Patent Searching and Data


Title:
LEVEL DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS6146613
Kind Code:
A
Abstract:

PURPOSE: To prevent a detection level from being fluctuated even if a threshold value of a MOSFET is fluctuated by using a constant voltage generating circuit of mirror circuit constitution and a comparator circuit.

CONSTITUTION: Since FETs Q15, Q17 of the constant voltage generating circuit 12 constitute a mirror circuit, an identical drain current flows and the same current flows to FETQ16, Q18. Since an FETQ14 of the comparator circuit 11 is in mirror connection with the FETQ18, the same drain current also flows. Since FETQ11, Q13 are in mirror connection, an identical current corresponding to a level of an input IN. When input voltage VIN< reference voltage VS, the level of an output OUT goes to L and when VIN>VS, the output goes to H. When VIN=VS, the output is equal to the VS. Since the reference voltage generating 12 and the comparator circuit 11 are of the same circuit constitution, even if the threshold level of the FETs is fluctuated, the detection level is not fluctuated.


Inventors:
OBATA HIROYUKI
Application Number:
JP16748084A
Publication Date:
March 06, 1986
Filing Date:
August 10, 1984
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03F3/343; G01R19/165; H03F3/34; H03F3/347; H03K5/08; H03K5/24; (IPC1-7): H03F3/343; H03K3/02
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)