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Title:
LEVEL METER CIRCUIT
Document Type and Number:
Japanese Patent JPS61217771
Kind Code:
A
Abstract:

PURPOSE: To achieve a higher accuracy, by providing a gate circuit which energizes an output circuit selectively according to the input signal level applied to an input terminal in response to the outputs of first and second level area discriminator circuits.

CONSTITUTION: When an input signal (e) is applied to an input terminal 1, a first level area discriminator circuit 2 discriminates which the input signal belongs to among multiple level areas obtained by dividing the fullscale. The signal (e) also is applied to a level shift circuit 3 to be shifted by levels according to the output of the circuit 2 and further, the output signal is amplified with a DC amplifier 4, the output of which 4 is inputted into a second level area discriminator 5, which discriminates which the input signal belongs to among the level areas further subdivided within the level range discriminated with the circuit 2. Then, outputs of the circuits 2 and 5 are applied to an output circuit group 7 through a gate circuit group 6 and the circuit group 7 is energized according to the combination of discrimination outputs. Then, the level output corresponding to the input signal is shown in a display 10.


Inventors:
OTANI KENJI
KAKEHI TATSUYA
Application Number:
JP5878085A
Publication Date:
September 27, 1986
Filing Date:
March 23, 1985
Export Citation:
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Assignee:
ROHM CO LTD
International Classes:
G01R19/165; G09G3/04; (IPC1-7): G01R19/165; G09G3/04
Domestic Patent References:
JP59059035B
Attorney, Agent or Firm:
Nakamura Shigenobu