To enable the high speed operation of a level shifter with its simplified constitution.

A low-amplitude logic signal is connected to one end of a capacitor 112 and one end of a capacitor 114, offset voltage generating TFTs 132, 134 are connected to the other end of the capacitor 112, offset voltage generating TFTs 136, 138 are connected to the other end of the capacitor 114, and TFTs 112, 124 are connected at a connection of an output end in series between a source voltage feed line and a reference voltage feed line for high-amplitude logic signals. The TFT 122 has a threshold voltage set not greater than offset voltages provided by the TFTs 132, 134, and the TFT 124 has a threshold voltage set not less than the offset voltages provided by the TFTs 136, 138.