Title:
LEVEL SHIFTER, SEMICONDUCTOR INTEGRATED CIRCUIT, AND INFORMATION PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JP3657243
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a level shifter which operates normally at a high operating frequency with a low power consumption.
SOLUTION: The level shifter comprises first and second level shifters 1, 2 with transistors MP3, MN5, having mutually connected drains and transistors MP4, MN6, having mutually connected drains. The first level shifter 1 has transistors MP3, MP4, having sources connected to a power voltage VDD and drains connected to gates of others and transistors MN3, MN4, having gates connected to signals SIN, SINB, drains, connected to the drains of the transistors MP3, MP4 and sources grounded. The second level shifter 2 has transistors MN5, MN6, having sources grounded and drains connected to gates of others and the transistors MP5, MP6, having sources connected to the power voltage VDD, gates connected to the signals SIN, SINB, and drains connected to the drains of the transistors MN5, MN6.
Inventors:
Junichi Aoki
Application Number:
JP2002191518A
Publication Date:
June 08, 2005
Filing Date:
June 28, 2002
Export Citation:
Assignee:
NEC Electronics Corporation
International Classes:
H03K19/0185; H03K3/012; H03K3/356; H03K19/0175; (IPC1-7): H03K19/0185
Domestic Patent References:
| JP6164365A | ||||
| JP59216328A | ||||
| JP2000244307A |
Attorney, Agent or Firm:
Seisei Nishimura