Title:
LID FOR SEALING SEMICONDUCTOR PACKAGE, PACKAGE USING THE SAME, AND MANUFACTURE OF SAID LID
Document Type and Number:
Japanese Patent JP3155146
Kind Code:
B2
Abstract:
PURPOSE: To easily manufacture a solder layer having solder layer thickness inclination or thickness difference, by arranging a thick part position and a thin part position of a solder layer, in the peripheral direction of a ceramic plate, and forming the ridge between them as a curve.
CONSTITUTION: A base metal layer 7 is formed in the peripheral part 3 on one surface of a ceramic plate 2, and a base metal layer 8 is formed on the side surface part 4. A solder layer 9 as a sealing member is formed on the base metal layer 7, and a solder layer 10 is formed on the base metal layer 8. A wide part and a narrow part of the metal layer are formed in the peripheral direction of the base metal layer 7 of the ceramic plate 2. As to the solder layer 9 on the base metal layer 7, the solder layer on the wide part of the base metal layer 7 is thicker than the solder layer of the narrow part. The ridge of the solder layer between both part positions is formed as a gentle curve. Thereby gas caused by the pressure rise of a semiconductor chip mounting part can be made to escape smoothly to the outside.
Inventors:
Yamamoto, Tetsuya
Yoshino, Hideyuki
Takahashi, Eiji
Hashimoto, Shizuteru
Yoshino, Hideyuki
Takahashi, Eiji
Hashimoto, Shizuteru
Application Number:
JP8757194A
Publication Date:
April 09, 2001
Filing Date:
March 31, 1994
Export Citation:
Assignee:
SUMITOMO KINZOKU CERAMICS:KK
International Classes:
B23K1/00; H01L23/02; H01L23/04; H01L23/10; H05K1/02; (IPC1-7): H01L23/02
Attorney, Agent or Firm:
中前 富士男