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Title:
LIFETIME EVALUATION METHOD FOR SEMICONDUCTOR SURFACE
Document Type and Number:
Japanese Patent JP08139146
Kind Code:
A
Abstract:

PURPOSE: To obtain a lifetime evaluation method for semiconductor surface in which the lifetime can be evaluated for a wafer having epitaxial structure at the thin semiconductor layer thereof and/or the vicinity thereof and noncontact, nondestructive evaluation of quality can be attained.

CONSTITUTION: The lifetime of a semiconductor wafer having a thin semiconductor layer on the major surface of a semiconductor substrate is evaluated at the thin semiconductor layer and/or the vicinity thereof. In such evaluation method, electron-hole parts are generated in the vicinity of the surface of thin semiconductor layer using an exciting light having energy higher than the bad gap of a semiconductor to be inspected. Intensity of a light emitted through recoupling of electron-hole pair is then detected at a specific wavelength and the lifetime at the thin semiconductor layer and/or the vicinity thereof is evaluated based on the intensity.


Inventors:
Hoshi, Ryoji
Kitagawara, Yutaka
Takenaka, Takuo
Application Number:
JP1994000279321
Publication Date:
May 31, 1996
Filing Date:
November 14, 1994
Export Citation:
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Assignee:
SHIN ETSU HANDOTAI CO LTD
International Classes:
G01N21/63; G01N21/66; G01R31/26; H01L21/66; G01N21/63; G01N21/62; G01R31/26; H01L21/66; (IPC1-7): H01L21/66; G01N21/63; G01N21/66