Title:
LIGHT DETECTION APPARATUS
Document Type and Number:
Japanese Patent JPH0254128
Kind Code:
A
Abstract:
PURPOSE:To prevent the erroneous operation of a peak value holding circuit by providing a light detector, a DC voltage offset cancelling circuit and a signal generation circuit. CONSTITUTION:An interference signal is inputted to a DC voltage offset cancelling circuit 12 to remove a DC component from said signal and subsequently amplified with a predetermining gain by an amplifier 13 to be inputted to a signal generation circuit 14. The circuit 14 compares the inputted amplified interference signal level with a preset threshold value and, when the input signal level is equal to or more than the threshold value, a reading start signal is outputted to a peak value holding circuit 16 for a predetermined time. The circuit 16 performs resetting operation with the input of the reading start signal to clear a held peak value and subsequently reads the peak value of the amplified interference signal to hold the same. Next, this peak value is compared with the held peak value and the larger peak value among both of them is held. When the output of the reading start signal from the circuit 14 is stopped, the circuit 16 stops peak value reading operation.
Inventors:
OISHI YASUBUMI
TAKAHASHI SHIRO
TAKAHASHI SHIRO
Application Number:
JP20595388A
Publication Date:
February 23, 1990
Filing Date:
August 19, 1988
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G01N21/27; G01J1/44; G01M11/02; (IPC1-7): G01J1/44; G01M11/02; G01N21/27
Domestic Patent References:
| JPS61102526A | 1986-05-21 |
Attorney, Agent or Firm:
Yoshitaka Yoshitaka
Next Patent: JPH0254129