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Patent Searching and Data


Title:
LINE DISCONNECTOR
Document Type and Number:
Japanese Patent JPH10271131
Kind Code:
A
Abstract:

To provide a line disconnector with which data can be separately outputted with high efficiency without expanding device scale from multiplexed data multiplexing preferential delay data and non-preferential delay data.

Buffers (BUF 1) 144 and (BUF 2) 145 to set the maximum number of cells to be held at a comparatively small value are provided corresponding to channels O and 1, and the preferential delay cells of channels 0 and 1 are respectively stored in these buffers (BUF 1) 144 and (BUF 2) 145. Besides, a buffer (BUF 3) 146 to set the maximum number of cells to be held commonly for the channels 0 and 1 at a large value is provided, and the non- preferential delay cells of channels 0 and 1 are stored in this buffer (BUF 3) 146 while being mixed. Then, the cells held in the buffers (BUF 1) 144 and (BUF 2) 145 are outputted preferentially rather than the cells held in the buffer (BUF 3) 146.


Inventors:
SUZUKI YASUYUKI
Application Number:
JP7576697A
Publication Date:
October 09, 1998
Filing Date:
March 27, 1997
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H04J3/16; H04L12/28; H04Q3/00; (IPC1-7): H04L12/28; H04J3/16; H04Q3/00
Attorney, Agent or Firm:
Kimura Takahisa