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Title:
LINE IDENTIFYING SYSTEM
Document Type and Number:
Japanese Patent JPS56120237
Kind Code:
A
Abstract:

PURPOSE: To enable line identification, by making different the virtual random signal applied to other channel by a given phase, to the virtual random signal applied to the reference channel.

CONSTITUTION: The signal inserted with the frame synchronising signal FS and converted in speed is separated into two systems with a serial-parallel conversion circuit SP. Further, one channel is scrambled with the virtual random signal generator PN1 at a scramble circuit SCR1. Other channel is scrambled with the signal delayed at a delay circuit DL1. Further, by keeping the delay time between the delay circuit DL1 at the transmission side and the delay circuit DL2 at the reception side equal each other, reception and reproduction can be made for correct line only.


Inventors:
MORITA TOSHIYUKI
HAYASHI MASAO
Application Number:
JP1980000023660
Publication Date:
September 21, 1981
Filing Date:
February 27, 1980
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04J3/00; H04B7/14; H04B7/15; H04B7/24; H04J3/14; H04K1/04; H04L1/00; H04L7/00; H04L27/18; H04W56/00; H04W84/12; (IPC1-7): H04B7/14; H04B7/24; H04J3/00; H04J3/14; H04L1/00; H04L11/00; H04L27/18
Domestic Patent References:
JPS5366318A1978-06-13
JPS5120620A1976-02-19



 
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