Title:
LINEAR INTERPOLATING METHOD AND CIRCUIT
Document Type and Number:
Japanese Patent JP3261729
Kind Code:
B2
Abstract:
PURPOSE: To decrease the number of coefficients used for interpolating operation and to reduce the capacity of a ROM with these built-in coefficients by performing the interpolating operation of the next error data by using data already calculated by the interpolating operation after the interpolating operation in the linear interpolating circuit.
CONSTITUTION: When performing the interpolating operation in the linear interpolating circuit, the operation is performed by using first-order held data in a shift register 5 for data, data selected from a shift register 1 for data by a selector 4 corresponding to a control signal from a flag decoder 3, and the coefficients built in a ROM 7 decided by the control signal from the flag decoder 3, and this arithmetic result is defined as interpolated data. In the next clock cycle, these interpolated data are temporarily held in the shift register 5 for data, and the next interpolating operation is performed.
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Inventors:
Takeo Doi
Super Yagishita
Yasunao Masuko
Tsuyoshi Takayama
Super Yagishita
Yasunao Masuko
Tsuyoshi Takayama
Application Number:
JP8179992A
Publication Date:
March 04, 2002
Filing Date:
April 03, 1992
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G11B20/18; H03M13/00; H03M13/37; (IPC1-7): H03M13/37
Domestic Patent References:
| JP63205862A | ||||
| JP6339990B1 | ||||
| JP6130344B2 |
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)