To provide a liquid crystal display controller which never lowers the operation efficiency of a CPU.

In the liquid crystal display controller equipped with a CPU_IF part 12 providing an interface with a CPU 10, a VRAM 16, a memory control part 14 performing access control over the VRAM, and a Barrett part 18 which converts the output of the memory control part into color data to be displayed on an LCD 24, a FIFO part equipped with a FIFO memory is installed between the memory control part and CPU_IF part in a path for writing the image data outputted by the CPU to the VRAM, and data needed to write the image data are stored in the FIFO part and the image data are stored in the VRAM under the control of the memory control part according to the data stored in the FIFO part.