To decrease the luminance difference of every other line of gate lines by compensating the effective voltage differences of vertical blanking periods odd lines and even lines.
This liquid crystal display device has timing circuits by which the shift registers are operated during the time of the vertical blanking period BK in such a manner that the common signal subjected to current alteration in one horizontal period is impressed to a counter electrode during the vertical blanking period BK and that the holding electrode signal of the same frequency, the same phase and the same amplitude as those of the common signal is impressed to a holding electrode during the vertical blanking period BK. Namely, the effective voltage differences of the vertical blanking periods odd lines and the even lines may be decreased by fluctuating a counter electrode potential Vcom and the voltage Vg1 at the time of gate off of the gate lines at every 1H, similarly to a data display period DA. The common signal is converted into AC for this purpose and is impressed via the common lines to the counter electrode and the gate off signal which is the same in the frequency, phase and amplitude as the common signal is impressed.
| JP2007188415 | DISPLAY PANEL WITH CONTACT CONTROL CIRCUIT |
| JPS62164020 | PRODUCTION OF LIQUID CRYSTAL DISPLAY DEVICE |
| WO/2010/038512 | DISPLAY DEVICE |
SHIBATA SUSUMU
AOKI HIRONORI
NAGANO SHINGO
Next Patent: FERROELECTRIC LIQUID CRYSTAL DEVICE