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Title:
メモリ装置およびメモリ装置を備えた液晶表示装置
Document Type and Number:
Japanese Patent JP5329670
Kind Code:
B2
Abstract:
A transistor (N1) has (i) a gate terminal which is connected to a word line (Xi(1)) and (ii) a first conduction terminal which is connected to a bit line (Yj). A transistor (N2) has (i) a gate terminal which is connected to the word line (Xi(2)) and (ii) a first conduction terminal which is connected to a node (PIX). A transistor (N3) has (i) a gate terminal which is connected to a node (MRY) and (ii) a first conduction terminal which is connected to the word line (Xi(2)). A transistor (N4) has (i) a gate terminal which is connected to the word line (Xi(3)), (ii) a first conduction terminal which is connected to a second conduction terminal of the transistor (N3), and (iii) a second conduction terminal which is connected to the node (PIX). A capacitor (Ca1) is formed between the node (PIX) and a reference electric potential wire (RL1), a capacitor (Cb1) is formed between the node (MRY) and the reference electric potential wire (RL1), and a capacitor (Cap1) is formed between the first conduction terminal of the transistor (N3) and the node (MRY). In a memory device which carries out a refresh operation in a data retention period following writing of a data signal electric potential, power consumption is reduced and the refresh operation is properly carried out.

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Inventors:
Shuji Nishi
Yuichiro Murakami
Furuta Shigeru
Sasaki Nei
Nariten Seijiro
Application Number:
JP2011531821A
Publication Date:
October 30, 2013
Filing Date:
May 18, 2010
Export Citation:
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Assignee:
Sharp Corporation
International Classes:
G11C11/406; G09G3/20; G09G3/36; G11C11/401; G11C11/405
Domestic Patent References:
JP2002207453A2002-07-26
JP2002229532A2002-08-16
JP2004163903A2004-06-10
JP2007034095A2007-02-08
JP2002207453A2002-07-26
JP2002229532A2002-08-16
JP2004163903A2004-06-10
JP2007034095A2007-02-08
Attorney, Agent or Firm:
Kenzo Hara International Patent Office



 
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