To provide a liquid crystal display device adopting a storage capacitor line driving system, achieving low power consumption for partial display in simple circuit configuration.
A polarity signal generating circuit 24 is formed of a first memory 241, a second memory 242, and an exclusive OR circuit 243. The first memory 241 stores first data showing the distinction between a display area where an image is displayed and a non-display area where an image is not displayed corresponding to each line. The first data are "1" in the display area and "0" in the non-display area. The second memory 242 is a memory storing second data showing the polarity of a polarity signal POL in one preceding frame, corresponding to each line. The first data read from the first memory 241 and the second data read from the second memory 242 are input to the exclusive OR circuit 243. The polarity signal POL is obtained from the exclusive OR circuit 243, and supplied to a storage capacitor line driving circuit 23.
Osamu Suzawa
Kazuhiko Miyasaka
Next Patent: IMPLEMENT FOR TRANSMITTING LIGHT EMISSION SIGNAL FOR EXTERNAL FLASH