To optimize the pin array of an integrated circuit element, to simplify the wiring of an interface circuit board and to lessen the bypassing and intricate drawing around of wiring by assorting and arranging input signal terminals, output signal terminals and mode setting terminals which respectively exist in plural pieces by each group.
Power source terminals P and grounding terminals G which respectively exist in plural pieces are allocated and arranged to the peripheral part of the integrated circuit element TCON. The input signal terminals I, output signal terminals O and mode setting terminals M which respectively exist in plural pieces are assorted and arranged by each group. Namely, the mode setting terminals M are gathered to the central part and the input signal terminals I and the output signal terminals O are gathered by one side each to the opposite side in the central part exclusive of the peripheral parts. The pin array of the integrated circuit element TCON is optimized in such a manner, by which the wiring of the circuit board is simplified and the bypassing and intricate drawing around of the wiring are reduced. The efficient wiring layout of the circuit board is easily embodied.
HASEGAWA KAORU
TORIYAMA YOSHIO
HITACHI DEVICE ENG
| JPS60186725A | 1985-09-24 |