To reduce the power consumption of a linearly sequential turned circuit by decoding address signals and successively selecting selective outputs from the lowermost position up to a lower half in the upper direction and from the uppermost position up to an upper half in the lower direction.

The linearly sequential addressing circuit is constituted of an address counter 1 and a decoding circuit 3 for receiving address signals 2 and outputting selective signals Q0 to Q15 to selective outputs 4. When a reset signal R is turned to '1', the address counter 1 resets all address signals A0 to A7 to '0'. In this case, the lowermost selective output Q0 outputs '1'. Thereafter each upper address is successively turned to '1' in each clock CK and the outputs Q2 to Q8 corresponding to the lower half of the selective outputs are successively selected. Thereafter address outputs are turned to '0' in each clock CK successively from the signal A6 in the lower address direction and corresponding selective outputs Q9 to Q15 are successively selected.