To display a small area without using any high-speed clock by providing a clock multiplying circuit which multiplies a reference clock set for minimum area display by a scale factor corresponding to the number of lines and the number of columns after a change in display format as the display format is changed and outputs the clock.

A timing circuit 9C' outputs an inputted clock to a RAM 9A and a ROM 9B as a timing signal CK(a) as it is and outputs a timing signal CK(b) once every 12 input clocks. The clock multiplying circuit 9E multiplies an externally inputted source oscillation clock and outputs it to the timing circuit 9C'. The clock multiplying circuit 9E automatically switches a multiplication number according to the number of display lines given from a CPU 8. Namely, the circuit outputs the source oscillation clock itself when the number of display lines is 1, a 2-fold clock of the source oscillation clock when 2, and a 4-fold clock of the source oscillation clock when 3.