Title:
LIQUID CRYSTAL DISPLAY
Document Type and Number:
Japanese Patent JP2023130388
Kind Code:
A
Abstract:
To provide a semiconductor device having a configuration capable of sufficiently reducing parasitic capacitance between wires.SOLUTION: In a thin film transistor of a bottom gate structure, an oxide insulating layer as a channel protection layer is formed on a part of an oxide semiconductor layer overlapping with a gate electrode layer, and when the oxide insulating layer is formed, an oxide insulating layer covering the periphery (including the side) of the oxide semiconductor layer is formed. The oxide insulating layer covering the periphery (including the side) of the oxide semiconductor increases the distance between the gate electrode layer and the wiring layers (source wiring layer, capacitor wiring layer, etc.) formed above or around the gate electrode layer to thereby reduce the parasitic capacitance. Since the oxide insulating layer covering the periphery of the oxide semiconductor layer is formed in the same step as that of the channel protection layer, the parasitic capacitance can be reduced without increasing the number of steps.SELECTED DRAWING: Figure 1
Inventors:
YAMAZAKI SHUNPEI
OHARA HIROKI
SASAKI TOSHINARI
NODA KOSEI
KUWABARA HIDEAKI
OHARA HIROKI
SASAKI TOSHINARI
NODA KOSEI
KUWABARA HIDEAKI
Application Number:
JP2023103887A
Publication Date:
September 20, 2023
Filing Date:
June 26, 2023
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB CO LTD
International Classes:
G09G3/36; G02F1/1368; G09F9/30; G09F9/35; G09G3/20; G11C19/28; H01L21/8234