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Patent Searching and Data


Title:
LOAD CONTROLLER FOR COMMON BUFFER MEMORY
Document Type and Number:
Japanese Patent JPH0630019
Kind Code:
A
Abstract:

PURPOSE: To accurately grasp the load state of a common buffer memory by providing a cell counter means and a maximum stored cell number storage means and controlling the load of the common buffer memory based on the information on the maximum stored cell number read out of the storage means.

CONSTITUTION: When a monitoring cycle timing signal 107 is generated from a call monitoring control part 41, the maximum stored cell number information 105 obtained in a monitoring cycle is transferred to the part 41 from a maximum stored cell number storage part 35. At the same time, the maximum stored cell number that is so far stored in the part 35 is cleared. Then the intra-buffer memory cell number information 102 is received from a cell counting part 34 and the intra-buffer memory maximum stored cell number is stored before the signal 107 arrives. Thus the load change can be statistically and correctly reflected even if the load applied to a common buffer memory 32 is suddenly changed due to the burst cell flows inputted to the input highways 11-1n. Therefore the load of the memory 32 can be accurately controlled based on the information 105.


Inventors:
TAKAHATA YOSHIAKI
Application Number:
JP17815592A
Publication Date:
February 04, 1994
Filing Date:
July 06, 1992
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
(IPC1-7): H04L12/48
Attorney, Agent or Firm:
Takehiko Suzue