To make shift data of a shift register be reliably latched by a latch circuit without errors even when a reference clock signal is sped up.
A load element drive circuit device 10A has a counter 16A for outputting an enable signal enable only for a period equivalent to 1 clock cycle when count value of a clock pulse of a reference clock signal CLK reaches 48, and a selection circuit 22 inserted between a shift register 12 and a latch circuit 14. The selection circuit 22 selects contents of first to 48th latch cells as first to 48th selection data respectively when there is no enable signal, and selects the shift data of the first to 48th data as first to Nth selection data when there is an enable signal. The latch circuit 14 is synchronized with the reference clock signal CLK and latches the first to the Nth selection data to the first to the Nth latch cells LA
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Shuichi Fukuda
Takashi Sasaki