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Title:
LOAD IMPEDANCE DETECTING CIRCUIT OF POWER AMPLIFIER
Document Type and Number:
Japanese Patent JPS59168708
Kind Code:
A
Abstract:

PURPOSE: To improve the protecting effect by forming a bridge circuit taking an emitter resistor and a load as sides for each transistor (TR) constituting a power amplifier and extracting its difference voltage as a signal related to a load impedance.

CONSTITUTION: An error amplifier A2 compares a positive and a negative power supply voltage with a reference voltage Vr and outputs the difference. A sawtooth wave generator SAW generates a sawtooth wave in synchronizing with a power frequency. A comparator CMP compares an output signal of an error amplifier A2 with the sawtooth wave and transmits a pulse signal. The conduction angle of thyristors SCR1, SCR2 is controlled by the pulse signal of the comparator CMP. The conductive angle of the thyristors SCR1 and SCR2 is changed by changing the reference voltage Vr or the gain of the error amplifier A2 in response to a DC voltage Vs so as to change the power supply voltage of output Trs Q1, Q2 or stop the supply.


Inventors:
KOBAYASHI HIDEHIRO
Application Number:
JP4289883A
Publication Date:
September 22, 1984
Filing Date:
March 14, 1983
Export Citation:
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Assignee:
FOSTER ELECTRIC CO LTD
International Classes:
H03F1/42; H03F1/52; (IPC1-7): H03F1/52
Attorney, Agent or Firm:
Ijima Fujiharu



 
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